The goal was to implement a 7nm block with over 2 million instances, targeting a frequency of 3.2GHz. The main constraints were area and power, requiring aggressive optimization strategies.
We employed a hierarchical floorplanning approach and utilized advanced partial-blockage techniques to ease congestion. For timing, we used useful skew and datapath optimization. IR drop was mitigated by strengthening the power grid with additional stripes.
The block was successfully closed with 0 DRC/LVS violations, meeting the timing signoff criteria across all corners.
