Scan Insertion & ATPG
DFT

Scan Insertion & ATPG

Implementing scan chains and generating test patterns to achieve high fault coverage for a complex S...

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AHB-Lite Protocol VIP
Design Verification

AHB-Lite Protocol VIP

Development of a comprehensive UVM-based Verification IP (VIP) for the AMBA AHB-Lite protocol, inclu...

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Block Level Implementation (7nm)
Physical Design

Block Level Implementation (7nm)

This case study details the complete Netlist to GDSII flow for a high-speed processor block using Sy...

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